Edge-prediction DTC and Clock-gating TDC Design for Ultra Low Power All Digital PLL

A 10-bit Digital to Time Converter with a Phase Noise Filter

The growing demand for asynchronous data communication leads to a growing demand for CDR systems to recover the sampling clock of the received data. The DTC in the CDR system is the main jitter source of the recovered data. A low-jitter DTC is required to generate data of low-jitter performance, calling for the application of a phase noise...