Low Power Bluetooth Baseband with a RISC-V Core for Autonomous Sensors using Chisel

The number of IoT devices and their applications is projected to continue increasing in the future, creating a demand for low-power wireless communications that allow IoT devices to either be connected directly to the internet or to use other devices as a back gate to it. BLE is already one of the most used wireless communication protocols for...

Implementation and Evaluation of Packed-SIMD Instructions for a RISC-V Processor

With the increase in the amount of data being gathered, the need for data processing is also rising. Furthermore, in addition to the proprietary ISAs that have been prevalent, the free and open RISC-V ISA has seen major interest. The modularity of the RISC-V ISA allows it to be extended with many instruction set extensions. One such extension...

Dynamic Hardware Binary Translator for ρ-VEX

The last years, there has been a increasing trend in embedded system and FPGA im-plementations for greater flexibility and also, a rising adaptation of heterogeneous plat-forms. These platforms often include FPGAs and embedded cores side by side.ρ-VEXcore, developed and maintained by the Computer Engineering group of TU Delft, is aVLIW processor...

A fault tolerant memory architecture for a RISC-V softcore

Technolution B.V. is developing a custom Reduced Instruction Set Computer (RISC)-V based softcore for implementation on a Field Programmable Gate Array (FPGA). Previously, the softcore used the memory residing on the FPGA only, which is very limited in capacity and limits scaling. To solve this problem, a connection is made from the softcore to...