A 10-bit Digital to Time Converter with a Phase Noise Filter

The growing demand for asynchronous data communication leads to a growing demand for CDR systems to recover the sampling clock of the received data. The DTC in the CDR system is the main jitter source of the recovered data. A low-jitter DTC is required to generate data of low-jitter performance, calling for the application of a phase noise...

A 10Gb/s PI-CDR design

In this thesis the design and analysis of a dual-loop phase interpolator(PI) clock and data recovery(CDR) with a Delay locked loop (DLL) as a reference loop will be discussed.

DLL Based Single Slope ADC For CMOS Image Sensor Column Readout

This thesis presents a Delay Locked Loop(DLL) based Single Slope ADC. Compared to the convertional Single Slope ADC, the readout speed is increased by 16 times. A DLL is designed with a start-controlled Phase Frequency Detector (PFD), a differential ended Charge Pump (CP) and fully differential Delay Cells (DC). The multi-stage comparator with...