A 24Gb/s PAM-4 Clock and Data Recovery Circuit With High Jitter Tolerance

The escalating demand for higher data rates in modern communication networks are pushing more transmitters and receivers to use a modulation technique with more spectral efficiency, like pulse amplitude modulation 4-level (PAM-4).<br/><br/>On the receiver side, phase detection for PAM-4 has proven to be difficult with most receivers using phase...

A 10Gb/s PI-CDR design

In this thesis the design and analysis of a dual-loop phase interpolator(PI) clock and data recovery(CDR) with a Delay locked loop (DLL) as a reference loop will be discussed.

A 10Gb/s Cryogenic Clock and Data Recovery System with Low Jitter

A key issue in current quantum computing interfaces is the dense interconnect between electronics at cryogenic temperature (CT) and room temperature (RT). Recently, progress has been made to move more control electronics from RT to CT, reducing interconnect overhead. The next step towards minimal interconnect is a direct wireline interface...

Source-Synchronous Interface with All-Digital Data Recovery: A Low-cost Efficient Design

This thesis proposes a low-cost high-efficiency source-synchronous interface for high-speed inter-chip communication. The interface is composed of LVDS transceivers as external I/O buffers, and an all-digital data recovery, which can calibrate the received data phase to be aligned to the 90^◦ phase of the received half-rate reference...