A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology

This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The...

A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow

We present a ring-oscillator-based sub-sampling phase-locked loop (PLL) using a generator-based design flow. A hybrid loop with a delta-sigma ($\Delta \Sigma$) modulator is applied to reduce the loop filter (LF) area and the control ripple. The generator automatically produces the ring oscillator and PLL to meet the provided specifications. The...

Intriguing luminescence properties of (Ba, Sr)₃Si₆O₉N₄: Eu²⁺ phosphors via modifying synthesis method and cation substitution

Synthesizing pure phase Ba₃Si₆O₉N₄ by the conventional solid-state reaction method is challenging because of easily formed secondary phase Ba₃Si₆O₁₂N₂ showing similar crystal structure. In this work, an alternative low temperature synthesis method is...