Li, Chao Chieh (author), Yuan, Min Shueh (author), Liao, Chia Chun (author), Chang, Chih Hsien (author), Lin, Yu Tso (author), Tsai, Tsung Hsien (author), Huang, Tien Chien (author), Liao, Hsien Yuan (author), Staszewski, R.B. (author) In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched...
journal article 2021
