Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs

Understanding the manufacturing defects in magnetic tunnel junctions (MTJs), which are the data-storing elements in STT-MRAMs, and their resultant faulty behaviors are crucial for developing high-quality test solutions. This paper introduces a new type of MTJ defect: synthetic anti-ferromagnet flip (SAFF) defect, wherein the magnetization in...

Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM

Understanding the defects in magnetic tunnel junctions (MTJs) and their faulty behaviors are paramount for developing high-quality tests for STT-MRAM. This paper characterizes and models intermediate (IM) state defects in MTJs; IM state manifests itself as an abnormal third resistive state, apart from the two bi-stable states of MTJ. We...

Device-Aware Test for Emerging Memories: Enabling Your Test Program for DPPB Level

This paper introduces a new test approach: device-aware test (DAT) for emerging memory technologies such as MRAM, RRAM, and PCM. The DAT approach enables accurate models of device defects to obtain realistic fault models, which are used to develop high-quality and optimized test solutions. This is demonstrated by an application of DAT to pinhole...

A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs

Manufacturing defects can cause faults in FinFET SRAMs. Of them, easy-to-detect (ETD) faults always cause incorrect behavior, and therefore are easily detected by applying sequences of write and read operations. However, hard-to-detect (HTD) faults may not cause incorrect behavior, only parametric deviations. Detection of these faults is of...

Impact of Magnetic Coupling and Density on STT-MRAM Performance

As a unique mechanism for MRAMs, magnetic coupling needs to be accounted for when designing memory arrays. This paper models both intra- and inter-cell magnetic coupling analytically for STT-MRAMs and investigates their impact on the write performance and retention of MTJ devices, which are the data-storing elements of STT-MRAMs. We present...

Device-Aware Test: A New Test Approach Towards DPPB Level

This paper proposes a new test approach that goes beyond cell-aware test, i.e., device-aware test. The approach consists of three steps: defect modeling, fault modeling, and test/DfT development. The defect modeling does not assume that a defect in a device (or a cell) can be modeled electrically as a linear resistor (as the traditional approach...