A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology

This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The...

A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow

We present a ring-oscillator-based sub-sampling phase-locked loop (PLL) using a generator-based design flow. A hybrid loop with a delta-sigma ($\Delta \Sigma$) modulator is applied to reduce the loop filter (LF) area and the control ripple. The generator automatically produces the ring oscillator and PLL to meet the provided specifications. The...

The application model of 3D cadastre in practical registration for real estate in China

Since the introduction of the concept of 3D cadastre, a great many of significant research results have been done. To promote the development of 3D cadatre, 3D cadastre working group sponsored by International Federation Surveyors (FIG) commissions 3 and 7 was organized by Delft University of Technology in 2001. This working group provides a...