A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO)...

A Carrier-based Two-Phase-Clamped DPWM Strategy With Zero-Sequence Voltage Injection for Three-Phase Quasi-Two-Stage Buck-Type Rectifiers

A three-phase buck-type rectifier features a step-down ac-dc conversion function, which is considered as a prominent solution for electric vehicle chargers and telecommunication systems integrated to the grid above 380 V line to line. However, traditional solutions for those applications employ cascaded architectures with an ac-dc boost-type...