Genetic Algorithm–Assisted Design of Redistribution Layer Vias for a Fan-Out Panel-Level SiC MOSFET Power Module Packaging

A fan-out panel-level packaging (FOPLP) with an embedded redistribution layer (RDL) via interconnection reduces the size, thermal resistance, and parasitic inductance of power module packaging. In this study, the effect of the RDL via size on the reliability of a FOPLP SiC MOSFET power module was investigated. To improve the thermal management...

Power-Efficiency Evolution of Capacitive Sensor Interfaces

Recent years have witnessed an improvement in the energy efficiency of capacitive sensor interfaces by more than three orders of magnitude. This article reviews the architectural and circuit innovations that have contributed to this progress. The fundamental limit on the energy consumption of capacitive sensor interfaces is discussed, as well...