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Poelma, R.H. (author), Van Zeijl, H. (author), Zhang, G. (author)The invention relates to vias for three dimensional (3D) stacking, packaging and heterogeneous integration of semi-conductor layers and wafers. In particular, the invention relates to a process for the manufacture of a via, to a via, to a 3D circuit and to a semiconductor device. Vias are interconnects used to vertically interconnect chips,...patent 2014