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Alfaro Barrantes, J.A. (author), Mastrangeli, Massimo (author), Thoen, David (author), Visser, Sten (author), Bueno Lopez, J. (author), Baselmans, J.J.A. (author), Sarro, Pasqualina M (author)
This paper describes the microfabrication and electrical characterization of aluminum-coated superconducting through-silicon vias (TSVs) with sharp superconducting transition above 1 K. The sharp superconducting transition was achieved by means of fully conformal and void-free DC-sputtering of the TSVs with Al, and is here demonstrated in up...
journal article 2021
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Alfaro Barrantes, J.A. (author), Mastrangeli, Massimo (author), Thoen, David (author), Bueno Lopez, J. (author), Baselmans, J.J.A. (author), Sarro, Pasqualina M (author)
We describe a microfabrication process that, thanks to a specifically tailored sidewall profile, enables for the first-time wafer-scale arrays of high-aspect ratio through-silicon vias (TSVs) coated with DC-sputtered Aluminum, achieving at once superconducting and CMOS-compatible 3D interconnects. Void-free conformal coating of up to 500μm...
conference paper 2020
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Alfaro, J.A. (author), Sberna, P.M. (author), Silvestri, C. (author), Mastrangeli, Massimo (author), Ishihara, R. (author), Sarro, Pasqualina M (author)
A novel, simple, low-cost method for the void-free filling of high aspect ratio (HAR) through-silicon-vias (TSVs) is presented. For the first-time pure indium, a type-I superconductor metal, is used to fill HAR vias, 300 to 500 μm in depth and 50 to 100 μm in diameter. The low electrical resistivity achieved without sintering, its...
conference paper 2018
document
Voicu, G.R. (author), Cotofana, S.D. (author)
Through-Silicon Vias (TSV) based 3D Stacked IC (3D-SIC) technology introduces new design opportunities for wide operand width addition units. Different from state of the art direct folding proposals we introduce two cost-effective 3D Stacked Hybrid Adders with identical tier structure, which potentially makes the manufacturing of hardware wide...
journal article 2016
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