Wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions for superconducting quantum processors

We investigate die-level and wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions, using multiple substrates with and without through-silicon vias (TSVs). Dolan junctions fabricated on planar substrates have the highest yield and lowest room-temperature conductance spread, equivalent to ∼ 100 M H z in...

Post-fabrication frequency trimming of coplanar-waveguide resonators in circuit QED quantum processors

We present the use of a set of airbridges to trim the frequency of microwave coplanar-waveguide (CPW) resonators post-fabrication. This method is compatible with the fabrication steps of conventional CPW airbridges and crossovers and increases device yield by allowing compensation of design and fabrication uncertainty with 100 MHz range and...

Realization of a quantum neural network using repeat-until-success circuits in a superconducting quantum processor

Artificial neural networks are becoming an integral part of digital solutions to complex problems. However, employing neural networks on quantum processors faces challenges related to the implementation of non-linear functions using quantum circuits. In this paper, we use repeat-until-success circuits enabled by real-time control-flow...

Variational preparation of finite-temperature states on a quantum computer

The preparation of thermal equilibrium states is important for the simulation of condensed matter and cosmology systems using a quantum computer. We present a method to prepare such mixed states with unitary operators and demonstrate this technique experimentally using a gate-based quantum processor. Our method targets the generation of...

High-Fidelity Controlled- Z Gate with Maximal Intermediate Leakage Operating at the Speed Limit in a Superconducting Quantum Processor

Simple tuneup of fast two-qubit gates is essential for the scaling of quantum processors. We introduce the sudden variant (SNZ) of the net zero scheme realizing controlled-Z (CZ) gates by flux control of transmon frequency. SNZ CZ gates realized in a multitransmon processor operate at the speed limit of transverse coupling between...