Temperature dependent trap characterisation and modelling of silicon carbide MOS capacitor

Due to the deficient passivation of the interface between silicon carbide and silicon dioxide, the defect-induced capture and release of trapped charges triggered by external Bias Temperature Stress (BTS) leads to parameter shifts and degraded device performance. This study models the trap-induced transient current in silicon carbide metal-oxide...

Design and Characterization of a Data Converter in a SiC CMOS Technology for Harsh Environment Sensing Applications

This work presents the design and characterization of an analog-to-digital converter (ADC) with silicon carbide (SiC) for sensing applications in harsh environments. The SiC-based ADC is implemented with the state-of-the-art low-voltage SiC complementary-metal-oxide-semiconductor (CMOS) technology developed by Fraunhofer IISB. Two types of...

Time-Dependent Dielectric Breakdown of 4H-SiC MOSFETs in CMOS Technology

The 4H-silicon carbide (SiC) exhibits excellent material characteristics, particularly in high-temperature, high-power, high-frequency applications. However, the reliability of SiC-based devices operating in harsh environments is a critical concern. While time-dependent dielectric breakdown (TDDB) in conventional SiC devices has been extensively...

Visible Blind Quadrant Sun Position Sensor in a Silicon Carbide Technology

In this paper, we present a quadrant sun position sensor microsystem device in a silicon carbide technology that operates in a field-of-view of ±33° and reaches a mean error of 1.9° in this range. This will allow, for the first time, an inherently visible blind sun position sensor in a CMOS compatible technology. Opto-electronic integration of...

Resistive and CTAT Temperature Sensors in a Silicon Carbide CMOS Technology

Accurately sensing the temperature in silicon carbide (power) devices is of great importance to their reliable operation. Here, temperature sensors by resistive and CMOS structures are fabricated and characterized in an open silicon carbide CMOS technology. Over a range of 25-200°C, doped design layers have negative temperature coefficients of...