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Cucu Laurenciu, N. (author)
Aggressive CMOS technology feature size down-scaling into the deca nanometer regime, while benefiting performance and yield, determined device characteristics variability increase w.r.t. their nominal values, which can lead to large spreads in delay, power, and robustness, and make devices more prone to aging and noise induced failures during in...
doctoral thesis 2017
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Wang, Y. (author)
Aggressive CMOS technology feature size scaling has been going on for the past decades, while the supply voltage is not proportionally scaled. Due to the increasing power density and electric field in the gate dielectric, the accelerating factors of failure mechanisms in nanoscale Integrated Circuits (ICs) have become more severe than ever. As a...
doctoral thesis 2013