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Yuan, S. (author), Zhang, Z. (author), Fieback, M. (author), Xun, H. (author), Marinissen, E. J. (author), Kar, G. S. (author), Rao, S. (author), Couet, S. (author), Taouil, M. (author), Hamdioui, S. (author)
The development of Spin-Transfer Torque Magnetic RAMs (STT-MRAMs) mass production requires high-quality test solutions. Accurate and appropriate fault modeling is crucial for the realization of such solutions. This paper targets fault modeling and test generation for all interconnect and contact defects in STT-MRAMs and shows that using the...
conference paper 2023
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Yuan, S. (author), Taouil, M. (author), Fieback, M. (author), Xun, H. (author), Marinissen, Erik Jan (author), Kar, Gouri Sankar (author), Rao, Sidharth (author), Couet, Sebastien (author), Hamdioui, S. (author)
The development of Spin-transfer torque magnetic RAM (STT-MRAM) mass production requires high-quality dedicated test solutions, for which understanding and modeling of manufacturing defects of the magnetic tunnel junction (MTJ) is crucial. This paper introduces and characterizes a new defect called Back-Hopping (BH); it also provides its...
conference paper 2023
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Aouichi, A. (author), Yuan, S. (author), Fieback, M. (author), Rao, Siddharth (author), Kim, Woojin (author), Marinissen, Erik Jan (author), Couet, Sebastien (author), Taouil, M. (author), Hamdioui, S. (author)
Spin-Transfer Torque Magnetic RAMs (STT-MRAMs) are on their way to commercialization. However, obtaining high-quality test and diagnosis solutions for STT-MRAMs is challenging due to the existence of unique defects in Magnetic Tunneling Junctions (MTJs). Recently, the Device-Aware Test (DA-Test) method has been put forward as an effective...
conference paper 2023
document
Gebregiorgis, A.B. (author), Wu, L. (author), Münch, Christopher (author), Rao, Siddharth (author), Tahoori, Mehdi B. (author), Hamdioui, S. (author)
STT-MRAM has long been a promising non-volatile memory solution for the embedded application space owing to its attractive characteristics such as non-volatility, low leakage, high endurance, and scalability. However, the operating requirements for high-performance computing (HPC) and low power (LP) applications involve different challenges....
conference paper 2022
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Wu, L. (author), Rao, Siddharth (author), Taouil, M. (author), Marinissen, Erik Jan (author), Kar, Gouri Sankar (author), Hamdioui, S. (author)
Understanding the manufacturing defects in magnetic tunnel junctions (MTJs), which are the data-storing elements in STT-MRAMs, and their resultant faulty behaviors are crucial for developing high-quality test solutions. This paper introduces a new type of MTJ defect: synthetic anti-ferromagnet flip (SAFF) defect, wherein the magnetization in...
conference paper 2021
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Wu, L. (author), Rao, Siddharth (author), Taouil, M. (author), Marinissen, Erik Jan (author), Kar, Gouri Sankar (author), Hamdioui, S. (author)
Understanding the defects in magnetic tunnel junctions (MTJs) and their faulty behaviors are paramount for developing high-quality tests for STT-MRAM. This paper characterizes and models intermediate (IM) state defects in MTJs; IM state manifests itself as an abnormal third resistive state, apart from the two bi-stable states of MTJ. We...
conference paper 2021
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Wu, L. (author), Rao, Siddharth (author), Taouil, M. (author), Marinissen, Erik Jan (author), Kar, Gouri Sankar (author), Hamdioui, S. (author)
As a unique mechanism for MRAMs, magnetic coupling needs to be accounted for when designing memory arrays. This paper models both intra- and inter-cell magnetic coupling analytically for STT-MRAMs and investigates their impact on the write performance and retention of MTJ devices, which are the data-storing elements of STT-MRAMs. We present...
conference paper 2020
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Fieback, M. (author), Wu, L. (author), Cardoso Medeiros, G. (author), Aziza, Hassen (author), Rao, S (author), Marinissen, Erik Jan (author), Taouil, M. (author), Hamdioui, S. (author)
This paper proposes a new test approach that goes beyond cell-aware test, i.e., device-aware test. The approach consists of three steps: defect modeling, fault modeling, and test/DfT development. The defect modeling does not assume that a defect in a device (or a cell) can be modeled electrically as a linear resistor (as the traditional approach...
conference paper 2019
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