Analysis and Design of a 2.5GS/s 6-bit SAR ADC with a 3-bit/cycle Resolving Scheme

The thesis analyzes the design challenges that arise when developing high-speed ADCs and shows, through an extensive architecture study, that the SAR topology can be used with a sampling rate of 2.5GS/s if asynchronous processing and a multi-bit per cycle approach are adopted. The transistor-level implementation and simulation of a 6-bit SAR ADC...

Combined Capacitance and Temperature to Digital Converter

This thesis describes the design and measurement of an IC which can digitize both capacitance and temperature. Capacitance sensing functionality is added to an existing Temperature to Digital Converter (TDC) without adding significant die area. Two kinds of baseline capacitance compensation techniques have been investigated and their performance...