Interfacing the ?-VEX with the µBlaze processor

Developments in reconfigurable platforms result in constantly increasing available area and improving technology. These improvements allow embedded systems to implement increasingly complicated systems. As a result the performance gap of processors build on FPGA technology compared to Semi-custom ASIC technology is decreasing. The down side of...

Interrupt support on the ?-VEX processor

In this thesis, we present a design of interrupt system upon an extensible and reconfigurable VLIW softcore processor: r-VEX. This interrupt system is designed and implemented in four mechanisms to match different application requirements in terms of the hardware consumption and performance issues (interrupt latency). On the other hand, due to...

General Purpose Computing with Reconfigurable Acceleration

In this thesis we describe a new generic approach for accelerating software functions using a reconfigurable device connected through a high-speed link to a general purpose system. In order for our solution to be generic, as opposed to related ISA extension approaches, we insert system calls into the original program to control the...

Fingerprint Verification on the VEX Processor

The speed gap between a processor realized in Semi-custom ASIC technology and a processor realized in FPGA technology is narrowing. In processor design, the approach is to define the microarchitecture of the processor and to design and implement it for executing an application domain. In this thesis, we have investigated the approach to design a...

Exploring and implementing a User Datagram Protocol/Internet Protocol stack within a small Field Programmable Gate Array

This thesis is part of the Arachne project which focusses on novel processor architectures that enable an ubiquitous and unobtrusive communication environment. Nowadays, the Internet provides many services of which some are envisioned to be utilized by stand alone devices. Access to those services requires an Internet Protocol stack (IP)...

PRAGMA: A Partial-Reconfigurable Audio Platform

As the area of applications for Field Programmable Gate Arrays, or FPGAs, continues to expand, designers are searching for new methods to enhance the flexibility and efficiency of these devices. A technique called Dynamic Partial Reconfiguration is based on a principle of reconfiguring a small region of the FPGA, while the remainder of the...

?-VEX: A reconfigurable and extensible VLIW processor

Increasingly more computing power is being demanded in the domain of multimedia applications. Computer architectures based on reconfigurable hardware are becoming more popular now that classical drawbacks are diminishing. FPGA are constantly improving in terms of performance and area, and provide a technology platform that allows fast and...

Run-Time Partial Reconfiguration on the Virtex-II Pro

Reconfigurable Computing entails the utilization of a general-purpose processor augmented with a reconfigurable hardware structure (e.g. a field-programmable gate array). Normally, a complete reconfiguration is needed to cha nge the functionality of the FPGA even when the change is only minor. Moreover, the complete chip needs to be halted to...