Accelerating Software Pipelines Using Streaming Caches

The trend of increasing performance by parallelism is followed by the adoption of heterogeneous systems. In order to allow more fine-tuned balancing between used thread- and instruction level parallelism, the heterogeneous ρ-VEX platform was developed. Pipelining has been a part of microprocessor development for decades to increase throughput of...

FPGA accelerated Facial Recognition

The ability to recognize faces is highly important in many areas of development. Though the years, the evolving technologies, enabled this process to be adapted in modern computer systems. These systems can be found in a wide variety of areas that yield significant impact. Therefore, there is an increasing demand for fast and accurate systems,...

A Dynamically Reconfigurable VLIW Processor and Cache Design with Precise Trap and Debug Support

This thesis describes the design and implementation of a VLIW processor and associated caches based on the ρ-VEX concept. An ρ-VEX processor must be dynamically (runtime) reconfigurable to behave as a single large processor, two medium-sized processors, or four small processors. This allows a scheduler to optimize for energy and/or performance...

Implementing Virtual Address Hardware Support on the ?-VEX Platform

The ?-VEX is a run-time reconfigurable Very Long Instruction Word (VLIW) processor. This unique processor allows separation of its issue lanes to form independently operating processing cores. Switching between these configuration during run-time allows optimizing the platform for the task(s) it is performing. Porting an Operating System (OS) to...

LLVM-based ?-VEX compiler

This thesis describes the development of an LLVM-based compiler for the ?-VEX processor. The ?-VEX processor is a runtime re- configurable VLIW processor. Currently, two compilers exist that target the ?-VEX processor: a HP-VEX compiler and a GCC-based compiler. We show that both compilers have disadvantages that are very dif- ficult to fix....

Modelling and Analysis of Execution Traces from Real-time Applications

The need for increased computing capability and more diverse hardware with its evermore complex topologies continues to grow. The use of multicore processors, which is quite established in the desktop computers, is gaining importance in the embedded systems for industrial applications. Because of the complexity of the environment and the special...

Design and analysis of a coherent memory sub-system for FPGA-based embedded systems

Cache coherence and memory consistency are of the most decisive and challenging issues in the design of shared-memory multi-core systems that influence both the correctness and performance of parallel programs. In this thesis, we identify and analyze the problem of designing a coherent/consistent memory subsystem in general and then focus on...

Design Partitioning for Custom Hardware Emulation

Hardware verification is a very important step of system design. Various techniques are used for this purpose one of which is hardware emulation. Hardware emulation is a very efficient and flexible technique with high speed performance in comparison to other approaches. Emulation using programmmable hardware can provide a very fast and feature...

Code Integrity Check targetting RISC Processors

Fault Detection for the Delfi Nanosatellite Programme

FPGA-ontwerp audio-netwerk voor VoIP-telefoon prototype: Ontwerprapport

In this thesis a design report is given for implementing Voip functionality on a FPGA. More specifically, the Voip functionality is coded in software (C) and executed on a Nios II softcore. This NiosII is a Verilog description which is programmed onto the vga with the specific drivers for the audio codec and network controller.

Interactieve website voor publicaties

This document describe the development cycle of the website for publications for the Delft University of Technology, Faculty Electrical Engeneering, Mathematics and Computer Science, Department Paralel and Distributed Systems. This include analysis, implementation, testing and the obstacles we came across during this cycle.