NoC characterization framework for design space exploration

A NoC is considered as the interconnect architecture for the future MPSoC. It should provide the required quality of service in terms of predictable guaranteed as well as best effort services to meet the application constraints. The application traffic patterns applied on a NoC is hard to predict due to dynamics of the application. A...

Physical design of a 3D router: Reducing the number of vertical connections and enabling asynchronous operation

With the use of multi-core architectures, the Network-on-Chip (NoC) became an important research topic. The most important benefit of a NoC compared to a communication bus is that it is scalable. The heart of the NoC is the router, which provides the communication between different computational units. This component is highly suitable to be a...

Dynamic loading and task migration for streaming applications on a composable system-on-chip

MPSoCs offer more and more processing capability to embedded systems. As a result, an increasing number of applications run on one system, sharing MPSoC resources. Some of these applications are streaming applications and may have real-time demands, e.g., guaranteed throughput, hence their temporal behavior has to be verified at design-time....

Design of a Crypto Core for Securing Intra System-on-Chip Communication

Interconnect centric security in multi core System-on-Chip (SoC) is an area of increasing concern. Monitoring and manipulation of the SoC interconnect yields great potential to bypass higher level security mechanisms. This thesis proposes SoC-TLS: a cryptographic hardware solution aimed to protect intra SoC communication against malicious IP and...

An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service

Prototyping Systems on Chip (SoC) on FPGA technology improves the time that the de- signer needs to spend in the verification stage when developing new systems or upgrading the existing ones. However, FPGA prototyping is very challenging due to the few resources available in this chips, and often the large designs do not fit into one single FPGA...