Searched for: department%3A%22Computer%255C%252BEngineering%22
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Fieback, M. (author), Cardoso Medeiros, G. (author), Wu, L. (author), Aziza, Hassen (author), Bishnoi, R.K. (author), Taouil, M. (author), Hamdioui, S. (author)
Resistive RAM (RRAM) is a promising technology to replace traditional technologies such as Flash, because of its low energy consumption, CMOS compatibility, and high density. Many companies are prototyping this technology to validate its potential. Bringing this technology to the market requires high-quality tests to ensure customer...
journal article 2022
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Aziza, Hassan (author), Hamdioui, S. (author), Fieback, M. (author), Taouil, M. (author), Moreau, Mathieu (author), Girard, Patrick (author), Virazel, Arnaud (author), Coulié, Karine (author)
RRAM density enhancement is essential not only to gain market share in the highly competitive emerging memory sector but also to enable future high-capacity and power-efficient brain-inspired systems, beyond the capabilities of today’s hardware. In this paper, a novel design scheme is proposed to realize reliable and uniform multi-level cell ...
journal article 2021
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Fieback, M. (author), Cardoso Medeiros, G. (author), Gebregiorgis, A.B. (author), Aziza, Hassen (author), Taouil, M. (author), Hamdioui, S. (author)
Industry is prototyping and commercializing Resistive Random Access Memories (RRAMs). Unfortunately, RRAM devices introduce new defects and faults. Hence, high-quality test solutions are urgently needed. Based on silicon measurements, this paper identifies a new RRAM unique fault, the Intermittent Undefined State Fault (IUSF); this fault causes...
conference paper 2021
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Aziza, H. (author), Moreau, M. (author), Fieback, M. (author), Taouil, M. (author), Hamdioui, S. (author)
Energy efficiency remains one of the main factors for improving the key performance markers of RRAMs to support IoT edge devices. This paper proposes a simple and feasible low power design scheme which can be used as a powerful tool for energy reduction in RRAM circuits. The design scheme is exclusively based on current control during write...
journal article 2020
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Fieback, M. (author), Wu, L. (author), Cardoso Medeiros, G. (author), Aziza, Hassen (author), Rao, S (author), Marinissen, Erik Jan (author), Taouil, M. (author), Hamdioui, S. (author)
This paper proposes a new test approach that goes beyond cell-aware test, i.e., device-aware test. The approach consists of three steps: defect modeling, fault modeling, and test/DfT development. The defect modeling does not assume that a defect in a device (or a cell) can be modeled electrically as a linear resistor (as the traditional approach...
conference paper 2019
Searched for: department%3A%22Computer%255C%252BEngineering%22
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