Design and Automated Implementation of a DfT Architecture for 3D-SICs

Three-dimensional stacked integrated circuits (3D-SICs) implemented with through silicon vias (TSVs) and micro-bumps open new horizons for faster, smaller and more energy-efficient chips. As all microelectronic structures, these 3D chips and their interconnects need to be tested for manufacturing defects. This thesis was executed in the context...

On 3D Stacked IC Yield Improvement and 3D-DfT Test Architecture

Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) is an emerging technology. It provides heterogeneous integration, higher performance and bandwidth, and lower power consumption. However, 3D-SICs suffer from lower compound yield, especially those based on Wafer-to-Wafer (W2W) stacking. In addition, testability of such...