Design of a Duty-Cycled Fractional-N ADPLL Based on Instantaneous Start-up LC DCO and High-precision DTCs

This thesis deals with the design of a duty-cycled, fractional-N and low-noise Phase Locked Loop (PLL) used for Ultra-Wideband applications in 40 nm process. This is the first-ever Duty-Cycled PLL (DCPLL) that is designed with an LC oscillator and brings down the noise record for DCPLLs by more than 1 order of magnitude. Due to the special...

An Ultra-Low-Power ADPLL for BLE Applications

In recent years, wireless personal area network (WPAN) applications have triggered the needs for low-cost and low-power PLLs which also provide good performance. All-digital phased-locked loops (ADPLLs) are preferred over their analog counterparts in nanoscale CMOS technology due to their flexibility, configurability, small area and easy...

DTC and TDC IC Design for Ultra-Low-Power ADPLL

The technology scaling favors the Digital PLLs, which is reconfigurable. In the traditional fractional-N ADPLL, whether counter-based or divider based, DCO and TDC are the main two power consuming blocks. Modifying the phase detection part based on phase prediction makes the architecture more energy-efficient. The new architecture leads to the...

Edge-prediction DTC and Clock-gating TDC Design for Ultra Low Power All Digital PLL

Low Power, All-Digital Fractional-N Frequency Synthesizers for Multi-GHz Applications

Despite their high degree of reconfigurability and friendliness to technology scaling, traditional ADPLL-based frequency synthesizers tend to come at the price of increased power consumption at their feedback path, compared to charge-pump based solutions. The main power consumption bottleneck is the TDC that operates at the high output frequency...

An Ultra-Low-Power ADPLL for WPAN Applications

RF PLLs for frequency synthesis and modulation consume a significant share of the total transceiver power, making sub-mW PLLs key to realize ulp WPAN radios. Compared to analog PLLs, all-digital phase-locked loops (ADPLLs) are preferred in nanoscale CMOS, as they offer benefits of smaller area, programmability, capability of extensive self...

Digitally Controlled Oscillator for WiMAX in 40 nm

This document describes the design and implementation of a digitally controlled oscillator for WiMAX application in 40 nm. This system contains two main blocks of an LC oscillator with a digitally controlled capacitor bank and a frequency-dividing chain containing frequency dividers with different division ratios and a frequency doubler to cover...

ADPLL Design for WiMAX

The frequency synthesizer, which functions as a local oscillator, is a critical block in the transceiver. It needs to meet very stringent specifications and consume as less power as possible. Design of a traditional charge-pump PLL as the frequency synthesizer in the advanced CMOS technologies in the transceiver of advanced communication systems...

Time-to-Digital Converter (TDC) for WiMAX ADPLL in State-of-The-Art 40-nm CMOS

WiMAX (Worldwide Interoperability for Microwave Access) is the emerging wireless technology standard of the near future, which enables high speed packet data access. To anticipate the future demands on WiMAX technology, we proposed an ADPLL (all-digital phase locked loop) solution for the WiMAX system. The developed ADPLL system has targeted...