A Capacitively Degenerated 100-dB Linear 20-150 MS/s Dynamic Amplifier

This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mV_pp,diff and 4 × gain, it achieves-100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice...

A Low-Power Class-AB Residue Amplifier for a 12bit 500MS/sec Pipeline ADC with Digital Calibration

This work mainly focuses on designing a low-power class-AB residue amplifier for a 12bit 500MS/sec pipeline ADC with digital calibration. A foreground ideal calibration test bench has been implemented in MATLAB to correct non-linearities of the amplifier up to the 5th order. A detailed comparison has been made between a class-A amplifier and a...