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Gong, J. (author), Charbon-Iwasaki-Charbon, E. (author), Sebastiano, F. (author), Babaie, M. (author)This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses...journal article 2022
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Pourmousavian, Naser (author), Kuo, Feng Wei (author), Siriburanon, Teerachot (author), Babaie, M. (author), Staszewski, R.B. (author)This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter ``doubles'' the supply voltage to all the digital circuitry and particularly regulates the time-to...journal article 2018