FPGA-based soft error correction for the memory of microcontrollers: A generic methodology to transparent soft error correction for the off-chip memory of microcontrollers operating in space

Manufacturers of CubeSats prefer the use of COTS electronic components such as microcontrollers (MCU) and SDRAM but these components are vulnerable to errors caused by radiation. A specific type of error caused by radiation are soft errors which can be corrected by Error Detection and Correction (EDAC) methods. Unfortunately, it is uncommon for...

Enabling High Performance Posit Arithmetic Applications Using Hardware Acceleration

The demand for higher precision arithmetic is increasing due to the rapid development of new computing paradigms. The novel posit number representation system, as introduced by John L. Gustafson, claims to be able to provide more accurate answers to mathematical problems with equal or less number of bits compared to the well-established IEEE 754...

Hardware acceleration of short-read mapping with the Burrows-Wheeler Aligner

Over the last decade, the costs of sequencing a human DNA molecule have been drastically reduced. It is therefore expected that the DNA sequence of patients will be used more often as a diagnostics tool in future clinical applications. However, DNA sequencers deliver millions of small fragments from random positions of the very large DNA string....

Acceleration of the Smith-Waterman algorithm for DNA sequence alignment using an FPGA platform

With the sequencing of DNA becoming cheaper and the resulting stack of data growing bigger, there is a big challenge for both engineer and biologist. Researchers are limited by their computational power. In this thesis, first an overview of sequence alignment algorithms will be given. Then a method to store the values of the similarity score...

A flexible high level modelling methodology for power and energy consumption

With the increasing complexity of current embedded applications, and the mobility required in embedded devices, new approaches are being proposed to optimize the power and the energy consumed by an application, at higher levels of abstraction levels and in earlier stages in a design flow. However, one essential part of a structured and guided...

?-VEX: A reconfigurable and extensible VLIW processor

Increasingly more computing power is being demanded in the domain of multimedia applications. Computer architectures based on reconfigurable hardware are becoming more popular now that classical drawbacks are diminishing. FPGA are constantly improving in terms of performance and area, and provide a technology platform that allows fast and...

A SoC solution for fingerprint minutiae extraction

Fingerprint identification or verification is used more often in civilian applications. In the near future, Automatic Fingerprint Identification Systems (AFIS) can be found on mobile phones or smartcards. Most AFIS are however computationally intensive, and are designed for execution on large systems such as PC's. The main bottleneck is the...

FPGA-ontwerp audio-netwerk voor VoIP-telefoon prototype: Ontwerprapport

In this thesis a design report is given for implementing Voip functionality on a FPGA. More specifically, the Voip functionality is coded in software (C) and executed on a Nios II softcore. This NiosII is a Verilog description which is programmed onto the vga with the specific drivers for the audio codec and network controller.

Finding hardware metrics from C code

Vanuit een groot aantal bedrijven is er een toenemende vraag naar snellere hardware. Het MOLEN-platform voorziet in die behoefte, doordat de architectuur bestaat uit een normale processor en een herprogrammeerbare chip. Hierdoor is een grote versnelling te behalen. Het omzetten van programmas naar deze architectuur is echter lastig en tijdrovend...