Spin-in of RISC-V Processors in Space Embedded Systems

The usage of terrestrial processors in space applications is not straightforward, as processors in space face unique challenges due to the effects of the space environment, like ionizing radiation causing Single Event Effects (SEEs). In the nineties, the European Space Agency chose the Scalable Processor ARChitecture (SPARC) Instruction Set...

A fault tolerant memory architecture for a RISC-V softcore

Technolution B.V. is developing a custom Reduced Instruction Set Computer (RISC)-V based softcore for implementation on a Field Programmable Gate Array (FPGA). Previously, the softcore used the memory residing on the FPGA only, which is very limited in capacity and limits scaling. To solve this problem, a connection is made from the softcore to...