Supply-Insensitive Frequency Synthesis for an LDO-Free Powering Scheme in SoCs

The scaling of CMOS technology in deep submicron process nodes is accompanied by the integration of more and more functional blocks of a system, whether digital or analog/RF, onto the same chip (i.e., system-onchip, SoC). These blocks would also place different requirements on their power supplies. To provide various static or dynamically...

Mutually Coupled Time-to-Digital Converters (TDCs) for Direct Time-of-Flight (dTOF) Image Sensors

Direct time-of-flight (dTOF) image sensors require accurate and robust timing references for precise depth calculation. On-chip timing references are well-known and understood, but for imaging systems where several thousands of pixels require seamless references, area and power consumption limit the use of more traditional synthesizers, such as...

An Ultra-Low-Power ADPLL for BLE Applications

In recent years, wireless personal area network (WPAN) applications have triggered the needs for low-cost and low-power PLLs which also provide good performance. All-digital phased-locked loops (ADPLLs) are preferred over their analog counterparts in nanoscale CMOS technology due to their flexibility, configurability, small area and easy...

Low Power, All-Digital Fractional-N Frequency Synthesizers for Multi-GHz Applications

Despite their high degree of reconfigurability and friendliness to technology scaling, traditional ADPLL-based frequency synthesizers tend to come at the price of increased power consumption at their feedback path, compared to charge-pump based solutions. The main power consumption bottleneck is the TDC that operates at the high output frequency...

Millimeter-Wave Digitally-Assisted Frequency Synthesizer in CMOS

ADPLL Design for WiMAX

The frequency synthesizer, which functions as a local oscillator, is a critical block in the transceiver. It needs to meet very stringent specifications and consume as less power as possible. Design of a traditional charge-pump PLL as the frequency synthesizer in the advanced CMOS technologies in the transceiver of advanced communication systems...

A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS

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