Ultra-Low Power On-Chip Oscillator: A 0.9-V 1.039-MHz 20.51-fJ/cycle oscillator in 28-nm CMOS with rail-to-rail output swing

An Ultra-Low Power Capacitive Readout Circuit for Wake-on-Touch Applications

Edge-prediction DTC and Clock-gating TDC Design for Ultra Low Power All Digital PLL

A Low Power 10-bit SAR ADC in a 45nm CMOS process

In this work a low power SAR ADC with 8.9 ENOB for wireless communication systems is presented. A capacitive charge redistribution DAC with a unit capacitor of 0.5fF is used. The implemented charge-sharing technique, allows the use of 2^(N-1) + 1 unit capacitors, instead of the conventional 2^N , thus decreasing the DAC area and the DAC...

Design of a fully integrated CMOS highly temperature stable frequency reference

A new fully integrated frequency reference has been designed, fabricated and measured. The goal of the design procedure has been high stability of the frequency over temperature variations. This should be achieved using a CMOS technology without MEMS and crystals, while being restricted by a very low power budget. The frequency is designed based...