High Step Coverage Interconnects By Printed Nanoparticles

The growing diversity in the used materials in semiconductor packaging provides challenges for achieving good interconnection. Particularly the very soft substrates, such as paper and polymers, and very hard, such as silicon carbide, offer unique challenges to wire-bonding or formation of vertical interconnects. Complementary technologies are...

Low temperature fine pitch vertical wafer level interconnection using copper nanoparticles

Nowadays, the demand for enhanced performance and reliability in micro and nano systems is growing, especially for fine pitch wafer level integration. Due to reliability and processing issues, lead containing solders are still allowed and being used in high demanding microelectronics bonding application. Potential for reliable environmental...