- document
- Wong, J.S.S.M. (author) doctoral thesis 2002
- document
- Sima, M. (author) doctoral thesis 2004
- document
-
Kuzmanov, G.K. (author)In this dissertation, we address high performance media processing based on a tightly coupled co-processor architectural paradigm. More specifically, we introduce a reconfigurable media augmentation of a general purpose processor and implement it into a fully operational processor prototype. The proposed media Molen prototype is implemented on...doctoral thesis 2004
- document
-
Meeuws, R.J. (author)Heterogeneous System Development needs Hardware/Software Partitioning performed early on in the development process. In order to do this early on predictions of hardware resource usage and delay are necessary. In this thesis a Quantitative Model is presented that can make early predictions to support the partitioning process. The model is based...master thesis 2007
- document
-
Sourdis, I. (author), Pnevmatikatos, D.N. (author), Vassiliadis, S. (author)In this paper, we consider hardware-based scanning and analyzing packets payload in order to detect hazardous contents.We present two pattern matching techniques to compare incoming packets against intrusion detection search patterns. The first approach, decoded partial CAM (DpCAM), predecodes incoming characters, aligns the decoded data, and...journal article 2007
- document
-
Moscu Panainte, E. (author)In this dissertation, we present the Molen compiler framework that targets reconfigurable architectures under the Molen Programming Paradigm. More specifically, we introduce a set of compiler optimizations that address one of the main shortcomings of the reconfigurable architectures, namely the reconfiguration overhead. The proposed...doctoral thesis 2007
- document
-
Raaijmakers, S.J. (author)Reconfigurable Computing entails the utilization of a general-purpose processor augmented with a reconfigurable hardware structure (e.g. a field-programmable gate array). Normally, a complete reconfiguration is needed to cha nge the functionality of the FPGA even when the change is only minor. Moreover, the complete chip needs to be halted to...master thesis 2007
- document
-
Calderon Rocabado, D.R.H. (author)In this dissertation, we address the design of multi-functional arithmetic units working with the most common fixed-point number representations, namely: unsigned, sign-magnitude, fractional, ten's and two's complement notations. The main design goal is to collapse multiple complex arithmetic operations into a single, universal arithmetic unit,...doctoral thesis 2007
- document
-
Kachris, C. (author)This dissertation presents our investigation on how to efficiently exploit reconfigurable hardware to design flexible, high performance, and power efficient network devices capable to adapt to varying processing requirements of network applications and traffic. The proposed reconfigurable network processing platform targets mainly access, edge,...doctoral thesis 2007
- document
-
Fernandes Chaves, R.J. (author)This thesis proposes a Secure Computing Module (SCM) for reconfigurable computing systems. SC provides a protected and reliable computational environment, where data security and protection against malicious attacks to the system is assured. SC is strongly based on encryption algorithms and on the attestation of the executed functions. The use...doctoral thesis 2007
- document
-
Sourdis, I. (author)This dissertation deals with essential issues pertaining to high performance processing for network security and deep packet inspection. The proposed solutions keep pace with the increasing number and complexity of known attack descriptions providing multi-Gbps processing rates. We advocate the use of reconfigurable hardware to provide...doctoral thesis 2007
- document
-
Hur, J.Y. (author), Wong, S. (author), Stefanov, T. (author)In this paper, we present a design and an analysis of customized crossbar schedulers for reconfigurable on-chip crossbar networks. In order to alleviate the scalability problem in a conventional crossbar network, we propose adaptive schedulers on customized crossbar ports. Specifically, we present a scheduler with a weighted round robin...journal article 2008
- document
-
Galuzzi, C. (author)In this dissertation, we address the design of algorithms for the automatic identi?cation and selection of complex application-speci?c instructions used to speed up the execution of applications on recon?gurable architectures. The computationally intensive portions of an application are analyzed and partitioned in segments of code to execute in...doctoral thesis 2009
- document
-
Doost Mohammady, R. (author)Cognitive Radios are currently a big challenge for the telecommunications industry. Many efforts are in progress to make communication radio systems as adaptive as possible such that they are aware of their environment and they are self configurable. An ultimate adaptive radio with the specified features is used to be called a Cognitive Radio. A...master thesis 2009
- document
-
Ahmadi, M. (author)In this dissertation, we present several techniques to achieve the high-performance processing in networked and grid environments. Many applications need a high-performance processing system to execute efficiently. High-performance processing mainly stems from parallelism. The parallel nature of grid computing is a very attractive solution to...doctoral thesis 2010
- document
-
Molenaar, B.A.M. (author)The application of lithium-ion batteries in electric vehicles provides some interesting advantages over lead-acid batteries, for instance the possibility to charge in 15 minutes. Fast charge currents are much larger than common charge currents, creating a need for uncommon hardware, for instance connectors with high current ratings. The client...master thesis 2010
- document
-
Fazlali, M. (author), Zakerolhosseini, A. (author), Gaydadjiev, G. (author)High latencies in FPGA reconfiguration are known as a major overhead in run-time reconfigurable systems. This overhead can be reduced by merging multiple data flow graphs representing different kernels of the original program into a single (merged) datapath that will be configured less often compared to the separate datapaths scenario. However,...journal article 2010
- document
-
Tzilis, S. (author)The ever-shrinking technology features have as a direct consequence the increase of defect density in VLSI chips. Going into the nano-scale era, the fabrication procedures cannot keep improving at the pace of the aforementioned shrinking of technology features. Fault Tolerance emerges as a much cheaper solution and it is imperative in the future...master thesis 2010
- document
-
Kobayashi, K. (author)Electronics systems in deep-submicron era face many new challenges. Increased intricacy of the manufacturing process will likely to increase the manufacturing defect while testing of those effect will be very challenging. Smaller feature size will also face new reliability issues due to phenomenas such as Joule heating and electromigration....master thesis 2010
- document
- Corina, M. (author) master thesis 2010