Metal-oxide-semiconductor field-effect transistors (MOSFETs) undergo fatigue degradation under high thermal and electrical stresses. This process results in changes in their parasitic parameters, which can be detected using frequency domain reflectometry (FDR). Frequency domain impedance analysis is employed to characterize the various quality states of Si and SiC MOSFETs obtained from accelerated aging experiments. Results demonstrate a consistent increase in parasitic resistance as the devices degrade. By determining the drain-source parasitic resistance at the self-resonant frequency (f_ SRF) and the drain-source on-resistance for MOSFETs with varying degradation degrees, positive linear numerical fitting equations (14)-(15) are established to predict MOSFET degradation under zero DC bias voltage. In addition, FDR technology is used to identify the drain parasitic resistance at the f_ SRF of MOSFET samples with different sizes of defects in the sintered silver layer. These results reveal a positive correlation between the quality of the sintered silver layer and Rrm DSRF. The proposed approach is an effective quality screening technology for power semiconductor devices without requiring power-on treatment.

Based on molecular dynamics (MD), in this study, a model was established to simulate the initial coating morphology of silver paste by using a random algorithm, and the effects of different sizes of particles on sintering porosity were also analyzed. The MD result reveals that compared with the sintering process using large-scale silver particles, the sintering process using multi-scale silver particles would enhance the densification under the same sintering conditions, which authenticates the feasibility of adding small silver particles to large-scale silver particles in theory. In addition, to further verify the feasibility of the multi-scale sintering, a semi in-situ observation was prepared for a sintering experiment using micro-nano multi-scale silver paste. The feasibility of multi-scale silver sintering is proved by theoretical and experimental means, which can provide a meaningful reference for optimizing the sintering process and the preparation of silver paste for die-attach in powering electronics industry. In addition, it is hoped that better progress can be made on this basis in the future.

With the emerging wide bandgap (WBG) semiconductor development, the increasing power density and efficiency of power electronic converters may cause more switching oscillation, electromagnetic interference noise, and additional power loss, further increasing the probability of device failure. Therefore, determining and quantifying the failure of a metal-oxide-semiconductor-field-effect transistor (MOSFET), which assembled using WBG semiconductor in some applications, is crucial to improving the reliability of a power converter. This study proposes a novel failure quantitative assessment approach based on MOSFET parasitic parameters. According to the two-port network theory, MOSFET is equivalent to some second-order RLC circuits composed of independent inductances, capacitances, and resistances in series. Then, the frequency-domain impedance associated with the physical failure of MOSFET is identified through frequency domain reflectometry. Accelerated aging and bond wires cut-off experiments are employed to obtain various quality states of the MOSFET device. Result shows that the MOSFET quality level and its number of bond wire lift-offs can be quantified effectively. Drain-to-source on-resistance (R_DS(on)) that normally represents the MOSFET quality shows a positive linear function relationship on drain-to-source parasitic resistance (R_D + R_S) during the quality degradation proceeding. This finding matches with the correlation established between R_{DS (on)} and R_D + R_S in theory. Meanwhile, source parasitic inductance (L_S) increases with the severity of bond wires faults, and even the slight fault shows a high sensitivity. The proposed approach would be an effective quality screening technology for power semiconductor devices without power on treatment, which can effectively avoid the impact of junction temperature and test conditions (current and voltage) on test results, and does not need to design additional test circuits. The test frequency range we used in this approach was 10–300 MHz, which to some extent is suitable for providing an on-line quality monitoring technology for high-frequency WBG power devices manufacturing.