Aging and Sintered Layer Defect Detection of Discrete MOSFETs Using Frequency Domain Reflectometry Associated With Parasitic Resistance

Journal Article (2024)
Authors

Ming Hui Yun (Guilin University of Electronic Technology)

Daoguo Yang (Guilin University of Electronic Technology)

Miao Cai (Guilin University of Electronic Technology)

Haidong Yan (Guilin University of Electronic Technology)

Jiabing Yu (Chongqing University)

Mengyuan Liu (Guilin University of Electronic Technology)

Siliang He (Guilin University of Electronic Technology)

Guo Qi Zhang (TU Delft - Electronic Components, Technology and Materials)

Research Group
Electronic Components, Technology and Materials
To reference this document use:
https://doi.org/10.1109/TDMR.2024.3363713
More Info
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Publication Year
2024
Language
English
Research Group
Electronic Components, Technology and Materials
Bibliographical Note
Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public. @en
Issue number
1
Volume number
24
Pages (from-to)
129-141
DOI:
https://doi.org/10.1109/TDMR.2024.3363713
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Abstract

Metal-oxide-semiconductor field-effect transistors (MOSFETs) undergo fatigue degradation under high thermal and electrical stresses. This process results in changes in their parasitic parameters, which can be detected using frequency domain reflectometry (FDR). Frequency domain impedance analysis is employed to characterize the various quality states of Si and SiC MOSFETs obtained from accelerated aging experiments. Results demonstrate a consistent increase in parasitic resistance as the devices degrade. By determining the drain-source parasitic resistance at the self-resonant frequency (f_ SRF) and the drain-source on-resistance for MOSFETs with varying degradation degrees, positive linear numerical fitting equations (14)-(15) are established to predict MOSFET degradation under zero DC bias voltage. In addition, FDR technology is used to identify the drain parasitic resistance at the f_ SRF of MOSFET samples with different sizes of defects in the sintered silver layer. These results reveal a positive correlation between the quality of the sintered silver layer and Rrm DSRF. The proposed approach is an effective quality screening technology for power semiconductor devices without requiring power-on treatment.

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