This paper presents a preliminary study of the set of trade-offs of UC-Berkley’s RISC-V instruction set architecture experiences, due to its lack of the Scaled Index addressing mode. The strong majority of the popular Instruction Sets such as x86, ARM, MIPS and PowerPC include relatively complex ways to calculate memory addresses (addressing modes). On the other hand, RISC-V notably lacks both the Indexed (LOAD rD,[rA+rB]) and Scaled Indexed (LOAD rD,[rA+rB*4]) addressing modes. This design choice impacts many aspects of the Instruction Set. As there’s no such thing as ‘the absolute best Instruction Set’, these aspects will be taken into account as trade-offs, which designers can use make educated decisions. The trade-offs which this study covers include the program size, implementation complexity and performance. These individual trade-offs will be analyzed at a surface level, intended more to explore the existence of anomalies than to go into depth into each topic due to limited time and resources.