Low-voltage and low-power front-end design is required for the safe and long-term monitoring of cardiac signals. To address the low-voltage challenge, this paper presents a subthreshold source-coupled logic (STSCL) based time-domain comparator designed in 180 nm CMOS process technology. At a low supply voltage of 0.8 V, the STSCL time-domain comparator consumes 2.3 μW at 1 MHz. Using 4 stages, the input referred noise and the offset of the comparator are 32 μVrms and 1.8 mV, respectively.