A Subthreshold Source-Coupled Logic based Time-Domain Comparator for SAR ADC based Cardiac Front-Ends

Conference paper (2019)

Authors

S. Rout Bio-Electronics - EEMCS
Samaneh Babayan-Mashhadi Eindhoven University of Technology
W.A. Serdijn Bio-Electronics - EEMCS
Research Group
Bio-Electronics (EEMCS) (TU Delft)
Copyright: © 2019 S. Rout, Samaneh Babayan-Mashhadi, W.A. Serdijn
DOI
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https://doi.org/10.1109/APCCAS47518.2019.8953136
Low-voltage Biosignal acquisition Source-coupled logic Time-domain comparator
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Published Date

01-11-2019

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Bio-Electronics

Abstract

Low-voltage and low-power front-end design is required for the safe and long-term monitoring of cardiac signals. To address the low-voltage challenge, this paper presents a subthreshold source-coupled logic (STSCL) based time-domain comparator designed in 180 nm CMOS process technology. At a low supply voltage of 0.8 V, the STSCL time-domain comparator consumes 2.3 μW at 1 MHz. Using 4 stages, the input referred noise and the offset of the comparator are 32 μVrms and 1.8 mV, respectively.