This thesis presents a BJT-based CMOS temperature-to-digital converter (TDC). With a continuous-time readout, the TDC avoids the kT/C noise limit incurred by previous discrete-time (switched-capacitor) TDCs. An energy-efficient BJT front-end generates single PTAT and CTAT currents for being digitized by a delta-sigma modulator through a linear charge-balancing operation. Simulated in a standard 0.18 um CMOS process, the TDC achieves a (3*sigma) inaccuracy of 0.13'C from -40'C to 125'C after one-point trimming. Moreover, the TDC achieves 4 mK resolution in a 202 millisecond conversion time, while consuming 4.9 uW. This corresponds to a resolution FoM of 15.7 pJ.K2.