With the ever-growing demand for higher data rates in both wireline and wireless systems, current complementary metal-oxide semiconductor (CMOS) digital-to-analog converters (DACs) must satisfy stringent bandwidth requirements. This poses major design challenges and often makes the DAC the main speed bottleneck. With CMOS technology nearing its fundamental scaling limits, conventional single-channel high-speed DAC architectures would struggle to keep up with the demand. In contrast, interleaved DAC architectures offer a promising alternative by using multiple lower-rate sub-DACs in parallel.

This thesis investigates frequency-interleaved digital-to-analog converters (FI-DACs) as a promising solution for overcoming bandwidth limitations. An overview of DAC interleaving concepts is presented, emphasizing the advantages of frequency interleaving compared to time-domain techniques. An analytical system-level analysis is then provided to describe the ideal operation of FI-DACs, particularly focusing on the analog part. Furthermore, the thesis investigates how power consumption can scale in FI-DAC architectures and highlights the associated design trade-offs.

The FI-DAC concept is experimentally validated using off-the-shelf components. The measurement results confirmed the feasibility of aggregating multiple sub-bands into a single continuous wideband output, while also highlighting practical challenges associated with the impairments of the analog circuitry. This thesis shows that FI-DACs could be a viable and scalable solution for future high-speed communication systems.