The number of IoT devices and their applications is projected to continue increasing in the future, creating a demand for low-power wireless communications that allow IoT devices to either be connected directly to the internet or to use other devices as a back gate to it. BLE is already one of the most used wireless communication protocols for this kind of devices, and its use is expected to continue increasing in the near future. Therefore the need for very low-power Bluetooth baseband designs arises. This thesis work presents a study on previous existing BLE baseband architectures. It proposes a new BLE baseband architecture where every non-bit-intensive function has been moved into software to fully make use of the efficient processor core in the SoC, and new functionalities have been added to the design in order to eliminate unnecessary communication between the baseband and processor. Furthermore, a novel non table based CRC error correction algorithm has been implemented in hardware and included in the bitstream processing chain in order to improve the reliability of the connection and therefore further reduce power consumption. In order to test the functionality of the proposed architecture, the bitstream processing blocks have been implemented and connected to a RISC-V processor core on the designed SoC. That was possible thanks to Chisel, a novel HDL based on Scala, and the Rocket-Chip generator that facilitates the task of integrating parameterizable cores and accelerators/coprocessors into an SoC design. The presented design has been simulated and implemented on a FPGA to test it and show its feasibility.