Better mechanical, thermal properties and longer lifetimes are needed for the die attach layer in high-power electronic packaging. As traditional Sn-Ag-Cu (SAC) solders have many limitations, the sintered nanosilver materials are becoming one of the substitutes for high-power electronic packaging. However, the high performance of sintered nanosilver materials is only achieved when its fine sintering densification is formed. This article investigates the sintering densification process of nanosilver particles based on the design of orthogonal experiments and sintering kinetics modeling in which both the macroproperties and micromorphology are linked and analyzed. The results lead to several conclusions, such as: 1) the orthogonal experiments consider the effects of sintering temperature, dwell time, and sample preparation pressure on the sintering relative shrinkage and relative density - the results show that the most critical impact factor on sintering densification is the sintering temperature. (2) In the sintering kinetic experiments, the sintering densification rates obtained by fitting the relative density versus dwell time curves during 175 °C-250 °C follow the Arrhenius model, and the apparent activation energy of sintering kinetics is calculated to be 36 kJ/mol, while it is calculated from the particle size is 38.1 kJ/mol. 3) Through modeling the relationship between particle size, line shrinkage, and porosity, the line shrinkage and porosity first increase at the initial stage, while the particle size increases, and the macroscopic volume decreases at the end of sintering, the porosity decreases.

As one of solid state lighting sources, wafer-level chip scale Light Emitting Diode (LED) packages has gained much attention, because of its compact size, high power and high optical performance. For this package to be effective, the solder layer plays the critical role in heat dissipation, mechanical support and electrical conductivity. Among all types of solder materials, Sn-3.0Ag-0.5Cu (SAC305) solder alloy is considered as one of best chip-attachment candidates due to its acceptable cost, good solderability, and favorable shear strength. However, such solder connections are prone to fatigue over time due to thermal or power cycling. This paper models the wafer level chip scale LEDs soldered on both aluminum oxide and aluminum substrates with SAC305 solder alloy. Thermal cycling conditions are simulated to assess the fatigue damage of the solder interconnection. Von Mises stress and plastic work density are utilized to represent the fatigue damage per cycle by using finite element analysis (FEA) method. Important design considerations include the effects of LED chip substrate, thickness of the solder interconnections, void ratio in the solder connections and PCB substrate. The result is a set of fatigue damage accumulation metrics.