Large-scale quantum computing holds promise for exponentially faster computation speed to address currently unsolvable problems. Nevertheless, biasing, driving and reading numerous physical qubits operating at cryogenic temperature remains an on-going challenge. In particular, the integration of cryogenic control and readout ICs appears mandatory to overcome the wiring bottleneck [1]-[3]. In this regard, the promising higher operating temperature (up to 1K) of silicon semiconductor qubits offers a more substantial cryogenic power budget, which could enable addressing larger qubit arrays with integrated cryogenic CMOS electronics. In the context of 100,000 qubits at 1K, the maximum power consumption allowed by cooling capability is about 1W within a compact footprint of just a few cm2, defining targets of <10μW/qubit consumption and <0.01mm2/qubit footprint. Focusing on the readout IC, the semiconductor-qubit coherence time also imposes a typical <100μs readout time, while requiring a Bit Error Rate (BER) below 10-3.

This paper proposes a comprehensive model of capacitive feedback transimpedance amplifiers, based on an analysis of the parasitics and non-idealities of the system. The proposed model is in good agreement with circuit simulations (less than 2% error on the gain and 18% on the bandwidth for large set of parameters), and allows to compute the analytical boundaries of the capacitive topology. Finally, a comparative assessment between capacitive and resistive topologies in terms of performance is proposed and highlights the salient performances of capacitive feedback transimpedance amplifiers.