This paper demonstrates the design process and performance prediction of a cryogenic 22 nm FDSOI circuit using a design-oriented model. The simplified EKV model is adopted to capture IV characteristics of short-channel transistors, for which parameters are extracted from cryogenic measurement of commercial FDSOI MOSFETs. When applied to a complete circuit, the model accurately predicts performances at various back-gate voltages and temperatures, achieving less than 1 % average absolute error. This validates the presented analytical approach, even under the stringent requirements of low-temperature operation, paving the way to exploiting rather than enduring cryogenic temperature effects on CMOS designs.

Spin qubits are a promising candidate for large-scale fault-tolerant quantum computing due to <1µm2 footprint per qubit, higher operating temperature (up to 1K [1]) and possible compatibility with industrial CMOS processes [2], [3]. However, the need for a simultaneous ~µs readout of thousands of devices is especially challenging in terms of power consumption and footprint per qubit [4], [5]. Frequency-domain multiplexed (FDM) reflectometry architectures using cryo-CMOS have been introduced in [6], [7], [8] but these circuits require bulky > 100µm2 inductors and do not match readout time specifications using actual quantum devices. Besides, current integrator readout schemes have been proposed [9], [10], but offer no scaling perspectives beyond time-domain multiplexing, leading to strong constraints in terms of bandwidth and power consumption. Recently, [4] introduced a capacitive-feedback transimpedance amplifier achieving an inductor-less FDM readout of two quantum dots [11]. Nevertheless, the demonstrated power consumption per qubit of 214µW/qubit remains too high to match the maximum heat dissipation allowed near quantum devices [12] in a large-scale perspective. Moreover, the used On-Off Keying (OOK) modulations are limited to one qubit per carrier, thus requiring high bandwidth and power consumption in order to read thousands of qubits.

Large-scale quantum computing holds promise for exponentially faster computation speed to address currently unsolvable problems. Nevertheless, biasing, driving and reading numerous physical qubits operating at cryogenic temperature remains an on-going challenge. In particular, the integration of cryogenic control and readout ICs appears mandatory to overcome the wiring bottleneck [1]-[3]. In this regard, the promising higher operating temperature (up to 1K) of silicon semiconductor qubits offers a more substantial cryogenic power budget, which could enable addressing larger qubit arrays with integrated cryogenic CMOS electronics. In the context of 100,000 qubits at 1K, the maximum power consumption allowed by cooling capability is about 1W within a compact footprint of just a few cm2, defining targets of <10μW/qubit consumption and <0.01mm2/qubit footprint. Focusing on the readout IC, the semiconductor-qubit coherence time also imposes a typical <100μs readout time, while requiring a Bit Error Rate (BER) below 10-3.

This paper demonstrates the first on-chip frequency multiplexed readout of two co-integrated single-electron transistors without the need for bulky resonators. We characterize single electron dynamics in both single electron transistors at 4.2K before validating their simultaneous readout within 2.2μs, achieving a 99.9% fidelity with a 1MHz frequency spacing. This experimental demonstration paves the way towards resonator-free large-scale quantum-classical architectures that would be required for future universal and reprogrammable quantum computers.

This paper proposes a comprehensive model of capacitive feedback transimpedance amplifiers, based on an analysis of the parasitics and non-idealities of the system. The proposed model is in good agreement with circuit simulations (less than 2% error on the gain and 18% on the bandwidth for large set of parameters), and allows to compute the analytical boundaries of the capacitive topology. Finally, a comparative assessment between capacitive and resistive topologies in terms of performance is proposed and highlights the salient performances of capacitive feedback transimpedance amplifiers.