This paper demonstrates the design process and performance prediction of a cryogenic 22 nm FDSOI circuit using a design-oriented model. The simplified EKV model is adopted to capture IV characteristics of short-channel transistors, for which parameters are extracted from cryogenic measurement of commercial FDSOI MOSFETs. When applied to a complete circuit, the model accurately predicts performances at various back-gate voltages and temperatures, achieving less than 1 % average absolute error. This validates the presented analytical approach, even under the stringent requirements of low-temperature operation, paving the way to exploiting rather than enduring cryogenic temperature effects on CMOS designs.

This paper provides a comprehensive analysis of the DC and RF behavior of HBTs, spanning temperatures from 350 to 3.8 K. It underscores the necessity of detailed studies for the design of RF circuits for quantum computing, including LNAs, VCOs, and mixers, due to the absence of cryogenic models. The DC gain shows betas of 800 at room temperature (RT) and 3000 at 3.8 K. RF characterization indicates a maximum fT of 500 GHz at 3.8 K and 300 GHz at RT. The proposed figure-of-merit, (gm.fT/Ic), typically used in CMOS design, is explored across the temperature range. The study reveals a noise equivalent temperature of sub-1 K at 3.8 K with source matching. The noise behavior of Si/SiGe:C HBTs within 0.13 μ m BiCMOS technology is characterized over 293 to 4 K and 10 kHz to 12 GHz. The analysis shows a significant increase in the flicker noise coefficient, K, and corner frequency reduction at 4 K. The high frequency parameter fT reaches 500 GHz, demonstrating better performance compared to advanced CMOS nodes. This research supports the modeling of HBTs that are critical for circuits operating at cryogenic temperatures. These models are particularly beneficial for designing classical-to-quantum interfaces.