This paper provides a comprehensive analysis of the DC and RF behavior of HBTs, spanning temperatures from 350 to 3.8 K. It underscores the necessity of detailed studies for the design of RF circuits for quantum computing, including LNAs, VCOs, and mixers, due to the absence of cryogenic models. The DC gain shows betas of 800 at room temperature (RT) and 3000 at 3.8 K. RF characterization indicates a maximum fT of 500 GHz at 3.8 K and 300 GHz at RT. The proposed figure-of-merit, (gm.fT/Ic), typically used in CMOS design, is explored across the temperature range. The study reveals a noise equivalent temperature of sub-1 K at 3.8 K with source matching. The noise behavior of Si/SiGe:C HBTs within 0.13 μ m BiCMOS technology is characterized over 293 to 4 K and 10 kHz to 12 GHz. The analysis shows a significant increase in the flicker noise coefficient, K, and corner frequency reduction at 4 K. The high frequency parameter fT reaches 500 GHz, demonstrating better performance compared to advanced CMOS nodes. This research supports the modeling of HBTs that are critical for circuits operating at cryogenic temperatures. These models are particularly beneficial for designing classical-to-quantum interfaces.

Quantum computers require classical electronics to ensure fault-tolerant operation. To address compactness and scalability, it was proposed to implement such electronics as integrated circuits operating at cryogenic temperatures close to those at which quantum bits (qubits) operate. Circulators are among the most common blocks used in the qubit readout chain, but they are currently discrete devices with a bulky footprint, thus preventing large-scale system integration. For this reason, we present here a detailed description of the first fully integrated CMOS circulator operating from 300 K down to 4.2 K to be an integral part of cryogenic quantum computing platforms. At 300 K, the circuit's operating frequency is centered around 6.5 GHz with 28% fractional bandwidth, and it has 2.2-dB insertion loss, 2.4-dB noise figure, and 18-dB isolation while consuming 2.5-mW core power. These results are achieved thanks to a fully passive architecture based on LC all-pass filters, which allows achieving a 1.6\times increase in fractional bandwidth and the lowest power consumption with respect to the state of the art while using only 0.45 mm² of core area. This allows miniaturization of circulators in power-constrained multi-qubit readout systems.

Cryogenic solid-state quantum processors require classical control and readout electronics; to achieve compactness and scalability, cryogenic integrated circuits have been recently proposed for this goal. Circulators are widely used in readout circuits, however they are typically discrete bulky devices, thus preventing miniaturization. To address this issue, we propose a fully integrated 40-nm CMOS 6.5-GHz circulator operating from 300 K to 4.2 K. At 300 K, it achieves a 2.2-dB insertion loss, an 18-dB isolation, and a 2.4-dB noise figure over the 1-dB bandwidth from 5.6 GHz to 7.4 GHz, with a core power of only 2.5 mW. This improves to 2.1 mW core power at 4.2 K, while showing 1.3-dB insertion loss and 17-dB isolation over the 1-dB bandwidth from 5.8 GHz to 7.6 GHz. The circuit achieves a record-low core power and a 1.6× wider fractional bandwidth than the state-of-the-art, thus allowing its use for multiple channels in power-constrained cryogenic refrigerators. These advances are enabled by a fully-passive architecture based on LC all-pass filters, allowing the use of a lower clock frequency than in prior art.