The development of the Internet of Things has given rise to enormous new industries and applications, including automobiles, smart healthcare systems, smart houses, etc, and the power supply has become the major constraint preventing them from further increasing logic speed. Thus, a SC(switch-capacitance) DC-DC converter with high efficiency, integration on-chip, and multiple voltage conversion ratio (VCRs) is significantly important.SAR(successive Approximation Register) SC was published in 2013, it realized 2n − 1 voltage conversion ratios with n 2:1 SC stage with the cost of charge sharing loss. In 2014, Recursive topology minimized charge-sharing loss by maximizing the connection to the power rail to improve efficiency. While both topologies only offer 7 VCRs for 3 stages, the new topology utilizing the voltage negative feedback technique has expanded this range to 79 ratios, including all p/q rational ratios from 1/2 to 15/16.Each ratio is written in the form Vout=A ∗ VDD − B ∗ Vout, and only three voltage negative feedback module(negators) are to be used :VDD −Vout,2VDD −Vout,−Vout.This paper presents an improved design to expand this VCR range to boost operation, achieving VCR from 15/16 to 16 times the input.
In total,3 2:1 SC stages and 3 negators are applied, with a total capacitance of 1.3nF. The
capacitance of 3 stages and negators are 130p,260p,520p, and 130p respectively. The system
was designed and fabricated in a 180-nm BCD process, the peak efficiency is achieved at a 2:1
ratio @20MHz, with an efficiency of 82.28%, reached load current =6.4mA. The layout area is
approximately 2.084mm2 , and the current density estimated is 3.07 mW/mm2. The design has remarkably expanded the 79 VCR options to both buck operation and boost operation