The ΔΣ analog-to-digital converter (ADC) is widely used in audio applications for its high resolution. However, it is less energy efficient compared to Nyquist Rate ADCs. The growing demand for portable and wearable devices poses a more stringent power-efficient requirement on the audio system, and the traditional ADCs architecture is hard to achieve both high linearity and high energy efficiency. Zoom ADC is a proven energy-efficient hybrid structure for high-resolution and high-linearity applications. It consists of a front-end successive approximation register (SAR) ADC as a coarse stage and ΔΣ modulator backend to take advantage of the energy efficiency of a SAR ADC and the high resolution of a ΔΣ. However, the conventional zoom ADC suffers from distortion due to the input-correlated quantization error from the coarse stage. The tonal behavior (also known as “fuzz”) degrades overall linearity. This thesis describes a low cost, calibration-free method to suppress the fuzz in the zoom ADC. It improves the SNDR by introducing a 1st order fully passive noise shaper with a dithering to the coarse SAR ADC, which reduces the correlation of its quantization error with the input. A prototype ADC has been implemented in standard 160 nm CMOS process. It achieves 104.4dB peak SNR, 103.8 dB SNDR and 106.5 dB dynamic range (DR) in the audio band (20Hz~20kHz) at an oversampling ratio (OSR) of 62.5. The ADC consumes 317 μW from a 1.8V supply, thus resulting in a Schreier FoM of 185 dB.