Frequency translation is required in any modern wireless communication systems. This is in large part due to the fact that the modulated signal is easy to transmit in radio frequency in the form of an electromagnetic wave, and the demodulated signal is easy to process in the baseband frequency by a powerful digital processor. Frequency synthesizers are required during this frequency translation process. Though the upcoming commercial communication (e.g., 5G) is continuing to propel the semiconductor market, the Internet of things (IoT) aimed at health monitoring, intelligent agriculture and environmental sensing, home automation and security sensing is gaining more and more momentum in recent years. It requires ultra-low computing power and very low-cost hardware, which challenges RF engineers to design low power and small-area wireless transceivers. Frequency synthesizers typically take up considerable silicon area and are one of most power-hungry blocks of these transceivers. This thesis aims to design a clock generation digital phase-locked loop (DPLL) for the Bluetooth Low Energy (BLE) standard for IoT applications. The DPLL should have a small area and low power consumption. Hence, a ring-oscillator (RO) -based fractional-N DPLL is implemented to generate the desired clock. A phase noise improvement technique is proposed to reduce the in-band phase noise of the DPLL by around 6dB. Furthermore, a fast reference calibration loop is implemented to mitigate the reference spur effectively. A prototype is fabricated in the TSMC LP 40nm CMOS process. Measurements show that the proposed RO-based fractional-N DPLL achieves 1.6ps integrated jitter, -45.8dBc fractional spur, -43.6dBc reference spur and 1.8-2.7GHz tuning range while consuming only 1.33mW power. The resulting figure of merit (FOM) of the implemented DPLL is -234.7dB, which is the best compared with the state-of-the-art RO-based fractional-N PLLs.