Hardware loops, also referred to as zero-overhead loops, are a hardware feature used to reduce loop overhead in embedded processors by replacing software loops with dedicated hardware state. Presently, hardware loop implementations specify tight restrictions on permitted loop layout and control flow, limiting their applicability. Furthermore, the loop information presented by hardware is typically not exploited by other microarchitectural components. This thesis investigates a design that extends the hardware loop mechanism of the CV32E40P RISC-V core and reuses hardware loop state as a source of execution information.
To evaluate this proposal’s efficacy, the compiler and hardware are extended to support compressed instructions and restricted internal branches within hardware loops. This increases the number of applicable Embench workloads from 9 to 16 (out of 19 total workloads). Basic hardware loop conversion reduces dynamic branch execution by ≈ 21.8%, increasing to ≈ 28.4% when branch-containing loops are supported. The resulting loop metadata is reused to guide an instruction loop buffer and a data prefetcher. The loop buffer exploits known loop boundaries to buffer and replay loop-body instructions, achieving a geometric-mean speedup of ≈ 1.53× over the evaluated extended-hardware-loop baseline with an identical memory hierarchy but no loop buffer. In contrast, using hardware loop activity to gate data prefetching reduces prefetch effectiveness on average, showing that loop membership alone is insufficient to classify memory accesses as profitable to prefetch. The complete architecture achieves a geometric-mean speedup of ≈ 1.59× relative to the evaluated two-level-cache software-loop baseline.
Field-programmable gate array (FPGA) implementation results separate the cost of the hint from the cost of its consumers. Extending and exposing the hardware loop state increases LUT usage by only ≈ 2.5% relative to the baseline core, whereas the loop buffer configuration increases LUT usage by ≈ 11.1% and the complete cache, loop buffer, and prefetching microarchitectural components occupy 99.73% of the target FPGA slices. These results indicate that hardware loop information can be a low-cost and effective microarchitectural hint for instruction reuse, but that the value of the hint depends strongly on the consumer and that the structures consuming it need not themselves be low cost. ... Read more

Term-rewriting super-optimisation during compilation uses rewrite rules in order to restructure a provided code expression into the optimal form, comparing different expressions using a cost function. To reduce the compilation time taken by term-rewriting, the ruleset can be optimised by combining rules that were commonly chained during previous optimisation runs. With an any-time super-optimiser a specialised ruleset makes it possible to attain the optimal code expression, under the ruleset constraints, with a lower time requirement.

We found rule chaining methods to be effective at reducing the time necessary to obtain the canonical form. The methods performed well on synthetic benchmarks, as well as ones representative of real C projects. The frequency of the chained rule use and their uniqueness compared to the other compound rules directly dictates how great of a performance improvement its addition provides. Optimised sets demonstrated poor generality, indicating over-specialisation. ... Read more