This work presents the design and simulation of a PVT-robust x16 gain dynamic open-loop inverter-based Gm-ratio residue-amplifier for high-speed SAR-assisted pipeline ADCs. The amplifier is designed in a 28 nm standard bulk CMOS process with a regulated 0.9 V power supply and simulated across a -20°C to 85°C temperature range. It achieves a power dissipation of 1.67 mW at 1.3 GHz, corresponding to a power-speed ratio of 1.28 mW/GHz, with less than ±5% gain variation throughout all temperature corners in typical conditions.

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Most academic and commercial tri-dimensional (3D) parasitic resistance extraction EDA/CAD tools rely on finite element methods (FEM) and are mainly suited to digital circuitry. In analog and mixed-signal (AMS) circuits, such as power converters and radio-frequency analog front-ends, the layout structures used for the metal interconnections become much more diversified and complex. This paper proposes an EDA/CAD tool, based on an innovative methodology for 3D parasitic resistance extraction, leveraged by image processing techniques and algorithms. Some practical examples are shown to demonstrate the attractiveness of the proposed tool. Moreover, since our tool efficiently works in the domains of 2D image processing, if an extensive database of layouts is provided and enough training is carried out, advanced deep-learning techniques can be straightforwardly employed, speeding up parasitic resistance extraction in highly complex AMS layouts.@en