A phase-domain analog-to-digital converter (PhADC) is a promising alternative to a pair of amplitude-domain in-phase and quadrature (IQ) ADCs for low power FSK/PSK demodulation, but due to the nonlinear amplitude-to-phase conversion, IQ offsets and gain mismatch can produce nonlinear phase distortions which that can lead to phase errors and an increase in bit-error rate (BER). An IQ offset and gain mismatch detection technique is developed for PhADCs and verified. The offset and gain mismatch is estimated by detecting the phase vector distribution imbalance among the four phase quadrants after the analog-to-phase conversion. A feedback path has been constructed between the PhADC output and the offset/mismatch compensation interface. The closed loop will help the compensation interface to settle to the proper compensation values of the offset and mismatch. Incorporating this cancellation loop in a receiver system can improve its sensitivity and robustness. In a conventional IQ ADC receiver we have two quantizations, i.e., one for I and one for Q, and then process the information to extract the phase. By contrast, the PhADC, due to its embedded demodulation attribute, performs only phase quantization. So only one quantization is needed. Because of its compactness, the hardware is simpler and thereby consumes less energy. Moreover the PhADC is immune to magnitude variations, because in an IQ ADC, amplitude quantization noise produces larger phase quantization noise at small vector magnitudes, while in a PhADC a larger vector has the same phase quantization error as a small vector. Because of these advantages the PhADC is a very good candidate for low power communication. A detection algorithm has been developed that detects the phase vector distribution imbalance between the left and right IQ complex half plane in case of I offset and between the top and bottom of IQ complex half plane in case of Q offset. Using this imbalance we can determine the sign and size of IQ offset. A similar approach has been done for IQ gain mismatch, where the phase vector distribution imbalance is detected between the four phase quadrants in the IQ complex plane. A mixed-signal approach, i.e., detecting the offset and mismatch in the digital domain and compensate in the analog domain. It is well known that in the IQ ADC receiver the offset and mismatch can be detected and calibrated if necessary before the amplitude is converted into phase in the digital domain, but in the PhADC receiver the offset and mismatch cannot be determined directly due to the absence of amplitude information. Here, we use phase information rather than amplitude information for detection and compensation. For this reason, we have created a direct mismatch and offset detection technique using the output phase signal of the PhADC. The relation between signal-to-noise power ratio (SNR) and its digital counter parts bit-energy-to-noise density (Eb/No) and symbol-energy-to-noise density (Es/No) is established and is used to show the effect of IQ offset and gain mismatch on the BER as a function of channel and phase quantization noise from the PhADC. It is shown that Eb/No and or Es/No are not the same as SNR and less understood ratios that are often confused with SNR. The relation between SNR and Eb/No, or for higher dimensions (i.e., multiple bits per symbol), the Es/No depends on the modulation parameters. For π/4 DQPSK modulation, the following relationship holds:Eb/No = SNR + 0.97 dB. An ideal PhADC receiver for π/4 DQPSK demodulation, with a noise-free channel, can tolerate a maximum IQ offset of 28 mV and a gain mismatch of ± 25 dB for a required BER of 10-5 according to the IEEE802.15.6 standard. But with a channel noise of SNR= 21dB these become 22 mV and ± 6 dB, respectively. A practical PhADC receiver with the same channel noise can tolerate a maximum IQ offset of 14mV and a gain mismatch of ± 3 dB. An approach is presented to convert the PhADC receiver analog channel select filter to a digital one for discrete modeling purposes in Matlab Simulink. First, the Laplace transfer functions of the filter stages and from those the overall Laplace transfer function of the total filter are derived. A mapping procedure is proposed to convert the continuous time domain Laplace transfer function to a discrete one.

Analog computation-in-memory (CIM) architecture alleviates massive data movement between the memory and the processor, thus promising great prospects to accelerate certain computational tasks in an energy-efficient manner. However, data converters involved in these architectures typically achieve the required computing accuracy at the expense of high area and energy footprint which can potentially determine CIM candidacy for low-power and compact edge-AI devices. In this work, we present a memory-periphery co-design to perform accurate A/D conversions of analog matrix-vector-multiplication (MVM) outputs. Here, we introduce a scheme where select-lines and bit-lines in the memory are virtually fixed to improve conversion accuracy and aid a ring-oscillator-based A/D conversion, equipped with component sharing and inter-matching of the reference blocks. In addition, we deploy a self-timed technique to further ensure high robustness addressing global design and cycle-to-cycle variations. Based on measurement results of a 4Kb CIM chip prototype equipped with TSMC 40nm, a relative accuracy of up to 99.71% is achieved with an energy efficiency of 115.1 TOPS/W and computational density of 12.1 TOPS/mm2 for the MNIST dataset. Thus, an improvement of up to 11.3X and 7.5X compared to the state-of-the-art, respectively.@en